[LLVMdev] Order of optimization: modulo scheduling & register allocation
ryanrbaird at gmail.com
Wed Jan 23 15:45:03 PST 2013
I was reading about the order of optimizations in the code generation stage
This is the part that's interesting to me:
3. SSA-based Machine Code
This optional stage consists of a series of machine-code optimizations
that operate on the SSA-form produced by the instruction selector.
Optimizations like* modulo-scheduling* or peephole optimization work here.
4. Register Allocation<http://llvm.org/docs/CodeGenerator.html#register-allocation>—
The target code is transformed from an infinite virtual register file
SSA form to the concrete register file used by the target. This
phase*introduces spill code
* and eliminates all virtual register references from the program.
If modulo scheduling happens before more code is introduced, how do we know
that we still have an optimal schedule? Is there another scheduling stage
during later optimization?
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