[LLVMdev] Instruction Constraints Question

dag at cray.com dag at cray.com
Wed Jan 23 13:07:48 PST 2013

We've discovered a problem in the AVX2 gather patterns X86InstrSSE.td.

According to the AVX2 manual, no two of the destination register, vector
index register and mask register can be the same.  The patterns in
X86InstrSSE.td are missing this constraint and it's possible to generate
an illegal instruction.

It doesn't look like TableGen supports Constraints beyond EARLY_CLOBBER
and TIED_TO.  We would need to add a constraint such as "$dst != $src1,
$dst != $mask, $src1 != $mask" to the current patterns to enforce the

Is there another mechanism to suport a constraint like this or is
hacking TableGen the best way to do it?  If the latter, does anyone have
a sense of how difficult this would be to implement?


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