[LLVMdev] Code Generation for Statically Pipelined Architecture

ryan baird ryanrbaird at gmail.com
Wed Jan 23 09:15:11 PST 2013

I'm working on a project with a machine language for a statically pipelined
architecture.  This article provides an overview of the idea:
http://www.cs.fsu.edu/~whalley/papers/cal11.pdf.  Right now, we're using
the VPO compiler to produce this assembly code.  We've been exploring using
LLVM as a front-end to provide high level optimization.

We'd like to know if there's a good way to go about producing this assembly
language directly.  The problem I'm looking at is that one instruction can
control multiple individual effects.  For example, the instruction "
M[ALUR2] = sw RS2; RS2 = r[20]; ALUR2 = ALUR2 add SE" does a store, a
register read, and an ALU operation (keeping intermediate values in
internal registers).  We have encoding restrictions that allow us to fit
such a group of effects into a 32 bit instruction.

What would be the best way to accomplish this code generation using LLVM?
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