[LLVMdev] Half Float fp16 Native Support

beat beatbm at gmail.com
Tue Jan 22 05:02:22 PST 2013

after a long time i managed to make a progress with this problem. i can store
and load fp16 as i16 in to some registers and do an add instruction. the
problem now is that this messes up the real i16 (short, unsigned short). 

i have 
def FADD_H : NemaCorePseudo< (outs HGR16:$fd), (ins HGR16:$fs, HGR16:$ft),
"add.h\t$fd, $fs, $ft", [(set (i16 HGR16:$fd),(i16 (f32_to_f16 (f32 (fadd
(f32 (f16_to_f32 (i16 HGR16:$fs))),                                                                                                                                                        
(f32 (f16_to_f32 (i16 HGR16:$ft))))))))]>;

so i can have a half floating point add two half point variables and seems
to work fine.

View this message in context: http://llvm.1065342.n5.nabble.com/Half-Float-fp16-Native-Support-tp50665p54026.html
Sent from the LLVM - Dev mailing list archive at Nabble.com.

More information about the llvm-dev mailing list