[LLVMdev] Splitting live ranges of half-defined registers

Krzysztof Parzyszek kparzysz at codeaurora.org
Mon Jan 14 14:09:17 PST 2013

On 1/14/2013 3:47 PM, Jakob Stoklund Olesen wrote:
> It shouldn't be causing any compile time failures, the VirtRegRewriter is adding <imp-def> operands for the wide register to make it look like it is live everywhere the virtual register was live:
>   vreg(64).low_half = vreg(32)  // vreg(64) = 64-bit register
> Should be rewritten as:
>   physreg(32) = other-physreg(32), physreg(64)<imp-def>
> In the worst case, you should get a 64-bit copy instruction where a 32-bit copy would have been sufficient.

As I mentioned off-mailing-list, for us this is often a lot worse than 
having a wider instruction.  To give the context for the list 
audience---the problem is that if the 32-bit subregisters (which are 
actually independent registers) are used as a register pair, then in 
instructions in that live range, these 32-bit registers will be aliased 
to the super-register (the register pair).  This, in turn, will cause 
false-dependencies between instructions that only access the 
(non-overlapping) 32-bit portions.

For us, tracking of individual lanes would solve this issue, and I 
believe that it would lead to a better code quality in general.  I am 
very interested in getting this effort going.


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