[LLVMdev] Sub-Register Allocation
kwwaters at gmail.com
Fri Jan 11 18:39:43 PST 2013
> LLVM's register coalescer and allocator don't try to reschedule
> instructions, which seems to be required here.
I think you're right. Looking at the instruction schedules before register
allocation, shows that it's scheduling the load before the zero move in one
case but not the other.
Is there an easy way I can trick the scheduler into putting these in the
right order? Perhaps by adding a scheduling dependency between the move
and the load?
-- Kenneth Waters
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