[LLVMdev] Getting MCInst "ins" and "outs"

Gordon Keiser gkeiser at arxan.com
Wed Jan 2 12:25:12 PST 2013

In this case Imm:14 is the condition code of the instruction;  14 is ARMCC::AL (always execute) and Reg:0 will normally show the input flags register, generally CPSR, if there is one (0 is NOREG).   STR can't write flags, but for an instruction that can, there would be another reg listed after that which would be either CPSR or NOREG depending on the "S" bit of the instruction.   

Hope that helps,
Gordon Keiser
Software Development Engineer
Arxan Technologies

> -----Original Message-----
> From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu]
> On Behalf Of Vladimir Pouzanov
> Sent: Sunday, December 23, 2012 6:35 PM
> To: llvmdev at cs.uiuc.edu
> Subject: [LLVMdev] Getting MCInst "ins" and "outs"
> Hi all.
> I'm looking for some way to do code analysis with LLVM. Can someone please
> give me a hint, if it is possible to query an MCInst for what are input operands
> and what are output operands?
> Small example.
> Consider we have an instruction:
>   str r1, [sp, #8]
> Being mapped into MCInst instance it has the following operands:
>   <MCOperand Reg:61>     <-- maps to reg r1
>   <MCOperand Reg:105>    <-- maps to reg sp
>   <MCOperand Imm:8>      <-- maps to immed #8
>   <MCOperand Imm:14>
>   <MCOperand Reg:0>
> Now, what are the two last operands (that are not actually present in
> disassembly)? And is it somehow possible to map the operands to
> OutOperandList/InOperandList found in the td definition?
> --
> Vladimir Pouzanov
> http://www.farcaller.net/
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> LLVMdev at cs.uiuc.edu         http://llvm.cs.uiuc.edu
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