[LLVMdev] DFAPacketizer

[Anshuman Dasgupta]

Jonas,


At this point, the DFA packetizer models a simple VLIW architecture and 
does not accommodate multiple stages. That's the reason for the behavior 
you're seeing.


-Anshu


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*From:*llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] 
*On Behalf Of *Jonas Paulsson
*Sent:* Monday, February 11, 2013 11:16 AM
*To:* llvmdev at cs.uiuc.edu
*Subject:* [LLVMdev] DFAPacketizer

Hi,

I am having problems writing the ProcessorItineraries list. As 
instructions on my VLIW target have varying size I want to model both 
cpu units and bundle bits as FUs. The following does not work, to my 
surprise:

InstrItinData<ALU, [InstrStage<1, [BITS1,BITS2, BITS3, BITS4], 0>,

InstrStage<1, [ALU1, ALU2]>]>

I want to express that there are two ALU's, and four bundle slots, and 
in this case while allocating this type of instructions several times, I 
would like to be allowed only two such instructions per cycle.

ResourceTracker->reserveResources();

ResourceTracker->reserveResources();

ResourceTracker->reserveResources();

ResourceTracker->reserveResources();

ResourceTracker->reserveResources();

DFAPacketizer.cpp:84: void llvm::DFAPacketizer::reserveResources(const 
llvm::MCInstrDesc*): Assertion `CachedTable.count(StateTrans) != 0' failed.

It seems to not want to worry about the alu's, but it is fine as long as 
there are any FU of the first row (BITS) available.

What is missing?

Thanks,

Jonas Paulsson

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