[LLVMdev] Switch instruction optimization

[Paweł Bylica]

Hello there,

I have a high level code which would look like that in C++:

enum E { A, B, C };

E int2e(long i) {
    switch(i) {
        case 0: return A;
        case 1: return B;
        case 2: return C;
        default: return A;
    }
}

It is compiled to this IR with O3 optimization:

define i64 @int2e(i64 %i_arg) #0 {
entry:
  switch i64 %i_arg, label %label_case1 [
    i64 2, label %label_case3
    i64 1, label %label_case2
  ]

label_case1:                                      ; preds = %entry,
%label_case3, %label_case2
  %merge = phi i64 [ %i_arg, %label_case2 ], [ %i_arg, %label_case3 ], [ 0,
%entry ]
  ret i64 %merge

label_case2:                                      ; preds = %entry
  br label %label_case1

label_case3:                                      ; preds = %entry
  br label %label_case1
}

In the result IR `phi` instruction has 3 branches, but two first of them
returns the same value. Shouln't it be optimized?

- Paweł
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