[LLVMdev] [global-isel] Random comments on Proposal for a global instruction selector

[Jakob Stoklund Olesen]

On Aug 9, 2013, at 2:16 AM, David Chisnall <David.Chisnall at cl.cam.ac.uk> wrote:

> How would you model the microMIPS/Thumb-1/RISC-V 16-bit (and, in some cases, x86) idea that a denser encoding can be used if you restrict register accesses to the bottom half of the register set?  The registers are still the same bank, and the set of operations is the same, but in some cases much more expensive (having to switch in and out of microMIPS mode, for example, is very expensive).  This problem hits multiple layers in the lowering process.  I don't have a good solution for it (nor a strong requirement for it, but if there's a design that will make it easier to solve in the future then that would be nice, as we and the people at Berkeley are going to be doing a reasonable amount of work with variable-length encodings over the coming years).

We already support Thumb-2 quite well with the CostPerUse field in register descriptors. The register allocator tries to use the cheap half of the register bank more often to allow the compact encoding to be used as much as possible. This also applies to the x86-64 REX prefix.

Having to switch CPU modes mid-function sounds more like a research project. I suppose you could model MIPS/microMIPS as two separate register banks, but you would at least need a custom bank selector pass.

Thanks,
/jakob