[LLVMdev] 64-bit add using 2 32-bit operations, guarantee of stuck together?

[Owen Anderson]

Glue operands only exist during the instruction selection and early scheduling (SelectionDAG) phase of code generation.  They're long gone by the time the MachineInstr scheduler or the register allocator sees your program.  They're mostly used for ensuring that the early scheduler always generates a legal schedule, since it has a hard time modeling non-dataflow dependencies.

For the later phases of codegen, you need to either explicitly describe your dependencies (for example, having an explicit carry bit physical register that one instruction produces and the other consumes), or use the pseudo-instruction escape valve.

--Owen


On Apr 15, 2013, at 10:09 PM, Sam Parker <S.Parker3 at lboro.ac.uk> wrote:

> Hi Jakob,
> 
> If glue operands are used by the scheduler to keep instructions together, why can't the register allocator also do this?
> 
> Regards,
> Sam
> 
> On 15/04/2013 23:12, Jakob Stoklund Olesen wrote:
>> On Apr 15, 2013, at 2:02 PM, Francois Pichet <pichet2000 at gmail.com> wrote:
>> 
>>> Hi,
>>> 
>>> Let's say we have a 32-bit architecture where 64-bit additions are done using 2 operations.
>>> 
>>> Instructions are defined as follow in TableGen:
>>>    defm ADD64  : ALU32<"add", 1, 1, addc>;
>>>    defm ADD64C : ALU32<"addrc", 1, 2, adde>;
>>> 
>>> 
>>> Let's assume that the carry bit is implicit and that the 2 operations must *always* be stuck together for the 64-bit add to work properly.
>>> Is there a default guarantee that nothing will ever be inserted between "add" and "addrc" or is there a flag/condition to set somewhere to have that guarantee?
>> The register allocator expects to be able to insert spill code and copies between any instructions, except terminators.
>> 
>> The only way around that is to use pseudo-instructions that are expanded after RA.
>> 
>> /jakob
>> 
>> _______________________________________________
>> LLVM Developers mailing list
>> LLVMdev at cs.uiuc.edu         http://llvm.cs.uiuc.edu
>> http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev
> 
> _______________________________________________
> LLVM Developers mailing list
> LLVMdev at cs.uiuc.edu         http://llvm.cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev