[LLVMdev] Problem with Store of i8 in a global address

Pedro Malagón malagon at die.upm.es
Fri Apr 12 11:47:35 PDT 2013


Hi,

I am creating a new backend for a custom microcontroller.
In order to create the backend I am modifying from Mips backend.

My architecture has a store instruction with direct address mode. It
accepts two arguments: source register and address (immediate). This
instruction is not available in Mips, but it is in Hexagon, so I copied
from Hexagon the following, adapting it to my registers:

- In ISelLowering.h: CONST32 and CONST32_GP
- In ISelLowering.cpp: LowerGlobalAddress
- In TargetObjectFile.cpp: isGlobalInSmallSection
- In InstrInfo.td:

def SDTmyCONST32 : SDTypeProfile<1, 1, [
                                            SDTCisVT<0, i32>,
                                            SDTCisVT<1, i32>,
                                            SDTCisPtrTy<0>]>;
def myCONST32 : SDNode<"myISD::CONST32",     SDTmyCONST32>;
def myCONST32_GP : SDNode<"myISD::CONST32_GP",     SDTmyCONST32>;

let PrintMethod = "printDMemOperand" in
  def globaladdress : Operand<i32>;

def STdb : STInst<(outs),
                               (ins globaladdress:$addr, GPR32:$ra),
                               "stdb\t$addr, $ra",
                               [],
                               IIStore>
{
  let mayStore = 1;
}

def : Pat<(atomic_store_8 (IcyflexCONST32_GP tglobaladdr:$global),
                          (i32 GPR32:$ra)),
          (STdb tglobaladdr:$global, (i32 GPR32:$ra))>;

def : Pat <(truncstorei8 (i32 GPR32:$ra),
                         (myCONST32_GP tglobaladdr:$global)),
      (STdb tglobaladdr:$global, (i32 GPR32:$ra))>;

However, this IR code is working for Hexagon and not for my
architecture, being Target Node #190
@j = common global i8 0, align 1

define i32 @main() nounwind {
entry:
  %retval = alloca i32, align 4
  store i32 0, i32* %retval
  store i8 8, i8* @j, align 1
  ret i32 1
}

...
0x9086908: ch = store 0x9086440, 0x9086880, 0x90865d8,
0x90863b8<ST1[@j], trunc to i8> [ID=10]
ISEL: Starting pattern match on root node: 0x9086908: ch = store
0x9086440, 0x9086880, 0x90865d8, 0x90863b8<ST1[@j], trunc to i8> [ID=10]
...
LLVM ERROR: Cannot select: 0x9086908: ch = store 0x9086440, 0x9086880,
0x90865d8, 0x90863b8<ST1[@j], trunc to i8> [ID=10]
  0x9086880: i16 = Constant<8> [ID=6]
  0x90865d8: i32 = <<Unknown Target Node #190>> 0x90864c8 [ID=9]
    0x90864c8: i32 = TargetGlobalAddress<i8* @j> 0 [ID=7]
  0x90863b8: i32 = undef [ORD=1] [ID=3]

Can any one give me a clue over the problem? Did I miss something when
getting Hexagon backend code for direct address mode?

Thanks,
Pedro


-- 
Pedro Malagón - Profesor ayudante
91 549 57 00 - ext. 4220
Departamento de Ingeniería Electrónica
Escuela Técnica Superior de Ingenieros de Telecomunicación
Universidad Politécnica de Madrid




More information about the llvm-dev mailing list