[LLVMdev] Promoting i1 to i32 does not work...

Tue Apr 2 07:49:53 PDT 2013

On Tue, Apr 02, 2013 at 04:25:04PM +0200, Jan Tlatlik wrote:
> Hi there,
> 
> I'm having a hard time with promoting operands from i1 to i32 in my
> backend...
> I have to register classes, VTs are i1 and i32. The i1 registers are
> only for predication and conditional jumps, so I want to use them with
> brcond, setcc.
> There are no instructions to directly load a value in an i1 register or
> to copy between i1 and i32, so I need the DAG Legalizing Pass to not
> generate any nodes with i1 operands. That's where the trouble starts.
> Occasionally, there are setcc's with i1 operands being legalized for any
> reason I don't get.
> I tried setOperationAction(ISD::SETCC, i1, Promote), but the i1 operands
> didn't get promoted...I looked through the dump and it seems the i1
> operands will be inserted after Initial selection DAG building, but
> before Type-Legalization.  So I wonder why they don't get promoted by
> the Legalization Pass?!
> 

The problem with this program is that
i32 = and x, 1 is being lowered to i1 = truncate x by the DAGCombiner.

The legalizer is correctly promoting the SETCC arguments to i32, but the
DAGCombiner is undoing this promotion, because it sees
i32 = zero_extend (truncate x) and optimizes out the zero_extend.

I think if you do setOperationAction(ISD::TRUNCATE, MVT::i1, Expand),
it should fix them problem.

Note that if you have added an i1 register class using addRegisterClass(),
the SelectionDAG will assume that all (with a few exceptions) i1
operations are legal unless you tell it otherwise.

-Tom

> I attached the shortened isel-dump, so if anyone could have a short look
> on that I would be very thankful!
> 
> Jan

> Initial selection DAG: BB#11 '_main:for.cond164.preheader'
> SelectionDAG has 17 nodes:
>   0x1f34090: ch = EntryToken [ORD=161]
> 
>     0x1f34090: <multiple use>
>       0x1f8d210: i32 = FrameIndex<2> [ORD=158]
> 
>       0x1f63860: i32 = Constant<32> [ORD=159]
> 
>     0x1f8ce10: i32 = add 0x1f8d210, 0x1f63860 [ORD=159]
> 
>     0x1f60d60: i32 = undef [ORD=161]
> 
>   0x1f5f040: i32,ch = load 0x1f34090, 0x1f8ce10, 0x1f60d60<LD4[%sunkaddr41](tbaa=!"int")> [ORD=161]
> 
>         0x1f34090: <multiple use>
>         0x1f5c000: i32 = Register %vreg11
> 
>         0x1f5f040: <multiple use>
>       0x1f63760: ch = CopyToReg 0x1f34090, 0x1f5c000, 0x1f5f040
> 
>           0x1f5f040: <multiple use>
>           0x1f5ed40: i32 = Constant<1> [ORD=162]
> 
>         0x1f8d010: i32 = and 0x1f5f040, 0x1f5ed40 [ORD=162]
> 
>         0x1f5f340: i32 = Constant<0> [ORD=163]
> 
>         0x1f5c300: ch = seteq [ORD=163]
> 
>       0x1f61b90: i1 = setcc 0x1f8d010, 0x1f5f340, 0x1f5c300 [ORD=163]
> 
>       0x1f5ca00: ch = BasicBlock<if.end187 0x1f87698>
> 
>     0x1f8d110: ch = brcond 0x1f63760, 0x1f61b90, 0x1f5ca00
> 
>     0x1f8c910: ch = BasicBlock<if.then174 0x1f875f0>
> 
>   0x1f61a90: ch = br 0x1f8d110, 0x1f8c910
> 
> 
> Optimized lowered selection DAG: BB#11 '_main:for.cond164.preheader'
> SelectionDAG has 16 nodes:
>   0x1f34090: ch = EntryToken [ORD=161]
> 
>     0x1f34090: <multiple use>
>       0x1f8d210: i32 = FrameIndex<2> [ORD=158]
> 
>       0x1f63860: i32 = Constant<32> [ORD=159]
> 
>     0x1f8ce10: i32 = add 0x1f8d210, 0x1f63860 [ORD=159]
> 
>     0x1f60d60: i32 = undef [ORD=161]
> 
>   0x1f5f040: i32,ch = load 0x1f34090, 0x1f8ce10, 0x1f60d60<LD4[%sunkaddr41](align=8)(tbaa=!"int")> [ORD=161]
> 
>         0x1f34090: <multiple use>
>         0x1f5c000: i32 = Register %vreg11
> 
>         0x1f5f040: <multiple use>
>       0x1f63760: ch = CopyToReg 0x1f34090, 0x1f5c000, 0x1f5f040
> 
>           0x1f5f040: <multiple use>
>         0x1f63660: i1 = truncate 0x1f5f040
> 
>         0x1f5ed40: i1 = Constant<-1>
> 
>         0x1f5f540: ch = setne
> 
>       0x1f5c300: i1 = setcc 0x1f63660, 0x1f5ed40, 0x1f5f540
> 
>       0x1f5ca00: ch = BasicBlock<if.end187 0x1f87698>
> 
>     0x1f8d110: ch = brcond 0x1f63760, 0x1f5c300, 0x1f5ca00
> 
>     0x1f8c910: ch = BasicBlock<if.then174 0x1f875f0>
> 
>   0x1f61a90: ch = br 0x1f8d110, 0x1f8c910
> 
> 
> Type-legalized selection DAG: BB#11 '_main:for.cond164.preheader'
> SelectionDAG has 16 nodes:
>   0x1f34090: ch = EntryToken [ORD=161] [ID=-3]
> 
>     0x1f34090: <multiple use>
>       0x1f8d210: i32 = FrameIndex<2> [ORD=158] [ID=-3]
> 
>       0x1f63860: i32 = Constant<32> [ORD=159] [ID=-3]
> 
>     0x1f8ce10: i32 = add 0x1f8d210, 0x1f63860 [ORD=159] [ID=-3]
> 
>     0x1f60d60: i32 = undef [ORD=161] [ID=-3]
> 
>   0x1f5f040: i32,ch = load 0x1f34090, 0x1f8ce10, 0x1f60d60<LD4[%sunkaddr41](align=8)(tbaa=!"int")> [ORD=161] [ID=-3]
> 
>         0x1f34090: <multiple use>
>         0x1f5c000: i32 = Register %vreg11 [ID=-3]
> 
>         0x1f5f040: <multiple use>
>       0x1f63760: ch = CopyToReg 0x1f34090, 0x1f5c000, 0x1f5f040 [ID=-3]
> 
>           0x1f5f040: <multiple use>
>         0x1f63660: i1 = truncate 0x1f5f040 [ID=-3]
> 
>         0x1f5ed40: i1 = Constant<-1> [ID=-3]
> 
>         0x1f5f540: ch = setne [ID=-3]
> 
>       0x1f5c300: i1 = setcc 0x1f63660, 0x1f5ed40, 0x1f5f540 [ID=-3]
> 
>       0x1f5ca00: ch = BasicBlock<if.end187 0x1f87698> [ID=-3]
> 
>     0x1f8d110: ch = brcond 0x1f63760, 0x1f5c300, 0x1f5ca00 [ID=-3]
> 
>     0x1f8c910: ch = BasicBlock<if.then174 0x1f875f0> [ID=-3]
> 
>   0x1f61a90: ch = br 0x1f8d110, 0x1f8c910 [ID=-3]
> 
> 
> Legalized selection DAG: BB#11 '_main:for.cond164.preheader'
> SelectionDAG has 17 nodes:
>   0x1f34090: ch = EntryToken [ORD=161] [ID=0]
> 
>     0x1f34090: <multiple use>
>       0x1f8d210: i32 = FrameIndex<2> [ORD=158] [ID=1]
> 
>       0x1f63860: i32 = Constant<32> [ORD=159] [ID=2]
> 
>     0x1f8ce10: i32 = add 0x1f8d210, 0x1f63860 [ORD=159] [ID=9]
> 
>     0x1f60d60: i32 = undef [ORD=161] [ID=3]
> 
>   0x1f5f040: i32,ch = load 0x1f34090, 0x1f8ce10, 0x1f60d60<LD4[%sunkaddr41](align=8)(tbaa=!"int")> [ORD=161] [ID=10]
> 
>         0x1f34090: <multiple use>
>         0x1f5c000: i32 = Register %vreg11 [ID=4]
> 
>         0x1f5f040: <multiple use>
>       0x1f63760: ch = CopyToReg 0x1f34090, 0x1f5c000, 0x1f5f040 [ID=12]
> 
>             0x1f5f040: <multiple use>
>           0x1f63660: i1 = truncate 0x1f5f040 [ID=11]
> 
>         0x1f8d010: i32 = zero_extend 0x1f63660
> 
>         0x1f5f940: i32 = Constant<1>
> 
>         0x1f5f540: ch = setne [ID=8]
> 
>       0x1f5f340: i1 = setcc 0x1f8d010, 0x1f5f940, 0x1f5f540
> 
>       0x1f5ca00: ch = BasicBlock<if.end187 0x1f87698> [ID=5]
> 
>     0x1f8d110: ch = brcond 0x1f63760, 0x1f5f340, 0x1f5ca00 [ID=14]
> 
>     0x1f8c910: ch = BasicBlock<if.then174 0x1f875f0> [ID=6]
> 
>   0x1f61a90: ch = br 0x1f8d110, 0x1f8c910 [ID=15]
> 
> 
> Optimized legalized selection DAG: BB#11 '_main:for.cond164.preheader'
> SelectionDAG has 16 nodes:
>   0x1f34090: ch = EntryToken [ORD=161] [ID=0]
> 
>     0x1f34090: <multiple use>
>       0x1f8d210: i32 = FrameIndex<2> [ORD=158] [ID=1]
> 
>       0x1f63860: i32 = Constant<32> [ORD=159] [ID=2]
> 
>     0x1f8ce10: i32 = add 0x1f8d210, 0x1f63860 [ORD=159] [ID=9]
> 
>     0x1f60d60: i32 = undef [ORD=161] [ID=3]
> 
>   0x1f5f040: i32,ch = load 0x1f34090, 0x1f8ce10, 0x1f60d60<LD4[%sunkaddr41](align=8)(tbaa=!"int")> [ORD=161] [ID=10]
> 
>         0x1f34090: <multiple use>
>         0x1f5c000: i32 = Register %vreg11 [ID=4]
> 
>         0x1f5f040: <multiple use>
>       0x1f63760: ch = CopyToReg 0x1f34090, 0x1f5c000, 0x1f5f040 [ID=12]
> 
>           0x1f5f040: <multiple use>
>         0x1f63660: i1 = truncate 0x1f5f040
> 
>         0x1f8d010: i1 = Constant<-1>
> 
>         0x1f5c300: ch = setne
> 
>       0x1f61b90: i1 = setcc 0x1f63660, 0x1f8d010, 0x1f5c300
> 
>       0x1f5ca00: ch = BasicBlock<if.end187 0x1f87698> [ID=5]
> 
>     0x1f8d110: ch = brcond 0x1f63760, 0x1f61b90, 0x1f5ca00 [ID=14]
> 
>     0x1f8c910: ch = BasicBlock<if.then174 0x1f875f0> [ID=6]
> 
>   0x1f61a90: ch = br 0x1f8d110, 0x1f8c910 [ID=15]
> 
> 
> ===== Instruction selection begins: BB#11 'for.cond164.preheader'
> ISEL: Starting pattern match on root node: 0x1f61a90: ch = br 0x1f8d110, 0x1f8c910 [ID=15]
> 
>   Initial Opcode index to 2296
>   Morphed node: 0x1f61a90: ch = BRrel 0x1f8c910, 0x1f8d110
> 
> ISEL: Match complete!
> ISEL: Starting pattern match on root node: 0x1f8d110: ch = brcond 0x1f63760, 0x1f61b90, 0x1f5ca00 [ID=14]
> 
>   Initial Opcode index to 2330
>   Morphed node: 0x1f8d110: ch = BRcondrel 0x1f61b90, 0x1f5ca00, 0x1f63760
> 
> ISEL: Match complete!
> ISEL: Starting pattern match on root node: 0x1f61b90: i1 = setcc 0x1f63660, 0x1f8d010, 0x1f5c300 [ID=13]
> 
>   Initial Opcode index to 1616
>   Match failed at index 1617
> LLVM ERROR: Cannot select: 0x1f61b90: i1 = setcc 0x1f63660, 0x1f8d010, 0x1f5c300 [ID=13]
>   0x1f63660: i1 = truncate 0x1f5f040 [ID=11]
>     0x1f5f040: i32,ch = load 0x1f34090, 0x1f8ce10, 0x1f60d60<LD4[%sunkaddr41](align=8)(tbaa=!"int")> [ORD=161] [ID=10]
>       0x1f8ce10: i32 = add 0x1f8d210, 0x1f63860 [ORD=159] [ID=9]
>         0x1f8d210: i32 = FrameIndex<2> [ORD=158] [ID=1]
>         0x1f63860: i32 = Constant<32> [ORD=159] [ID=2]
>       0x1f60d60: i32 = undef [ORD=161] [ID=3]
>   0x1f8d010: i1 = Constant<-1> [ID=7]
> In function: _main

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