[LLVMdev] mips16 puzzle

Reed Kotler rkotler at mips.com
Wed Sep 26 04:37:42 PDT 2012

I thought of one solution.

If we always copy SP to a virtual register during the function prologue, 
then if we see a use of addr in a store/load byte/halfword instruction, 
then we can change the register from SP to be this virtual register.

Then I think that all the usual llvm optimizations will save us; i.e. 
the copy will never occur if the virtual register is not accessed and in 
addition the copy will get moved closer to the actual access.

It makes intuitive sense to me to make the copy during the prologue, 
because that is when SP is modified.

On 09/25/2012 09:34 PM, Reed Kotler wrote:
> We already divided out our classes as you did for ARM.
> The problem here is that we have a store/load byte/halfword to/from a
> Frame object.
> We know at that time that it's not going to be possible to store it
> using  SP because there is only such instructions for store/load of a word.
> What we would want to do is to move SP into a Mips 16 register and then
> do a indexed load/store off of that register.when we finally create the
> load/store byte/word instruction.
> Hopefully then the aliased virtual register could be shared with other
> such virtual registers since SP does not change after the function
> prologue.
> gcc mips actually avoids this problem by always allocating one of the
> mips 16 registers as a sort of stack pointer, it's actually at a mid
> point in the functions stack frame.
> Reed
> On 09/24/2012 12:37 PM, Jim Grosbach wrote:
>> On Sep 20, 2012, at 11:44 PM, Reed Kotler <rkotler at mips.com> wrote:
>>> Actually, SP is already not in the mips 16 register class but there
>>> is some C++ code that is common to mips32, mips64 and mips16 that is
>>> wanting to use SP. It's kind of awkward but does work except in this
>>> case of load/store haflword and byte to stack objects.
>> ARM has a similar problem. The InstrInfo classes should be factored
>> out so that the targets have separate implementations where
>> appropriate. See ARMBaseInstrInfo, ARMInstrInfo, Thumb1InstrInfo and
>> Thumb2InstrInfo. Similarly, the FrameLowering classes.
>> If you're sharing that code between the various targets, it sounds
>> like there's some very significant architectural problems in your
>> port, to be honest.
>>> Maybe I'm shooting myself in the foot there. I don't know that code
>>> too well so maybe I need to look into it.
>>> There are some places where we use C++ code that I think we could use
>>> just td files or maybe in some cases add some small extensions to
>>> tablegen.
>>> Right now I'm just starting to debug and push upstream the whole mips
>>> 16 port and am at about 65% passing all single source and 25% of
>>> multi source tests.
>> It really should have been developed directly on trunk rather than
>> trying to push it upstream after the fact. Doing it this way is more
>> pain for everyone.
>>> On 09/20/2012 11:03 PM, Owen Anderson wrote:
>>>> Reed,
>>>> It's not clear to me that you need to do anything special here.  If
>>>> you define your MIPS16 register class as not containing SP, then any
>>>> MIPS16 instructions that get selected and want to read from SP
>>>> should get a COPY inserted from SP to a MIPS16 vreg.  The coalescer
>>>> should, ideally, get rid of extraneous copies for you.
>>>> --Owen
>>>> On Sep 20, 2012, at 10:48 PM, Reed Kotler <rkotler at mips.com> wrote:
>>>>> Trying to think of a clever way to do something....
>>>>> On Mips 16, the SP (stack pointer) is not a directly accessible
>>>>> register in most instructions.
>>>>> There is a way to move to and from mips 16 registers (subset of
>>>>> mips32) and mips32 registers.
>>>>> For the load/store word instructions, there are forms which
>>>>> implicitly take SP.
>>>>> However, for store/load byte and store/load halfword, there is no
>>>>> such instruction.
>>>>> In such cases, if I were writing assembly language code, I would
>>>>> move SP to a mips 16 register and then use it to do the store/load
>>>>> byte/haflword.
>>>>> It also then becomes a common subexpression because there may be
>>>>> multiple such accesses.
>>>>> It's like a temporary register alias.
>>>>> Add, Sub also have a way to reference memory using mips16 registers
>>>>> as a base address, so various operators on stack data are simplified.
>>>>> Any thoughts?
>>>>> Many ways to do this but I like simple ways. :)
>>>>> Tia.
>>>>> Reed
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