[LLVMdev] RE : Question about LLVM NEON intrinsics
sebastien.deldon at st.com
Fri Sep 21 03:19:46 PDT 2012
I guess one solution could be to define LLVM max intrinsic and have LLVM backends generating the appropriate instructions (using SSE inst for x86, NEON for ARM etc.).
> -----Original Message-----
> From: rengolin at gmail.com [mailto:rengolin at gmail.com] On Behalf Of
> Renato Golin
> Sent: Friday, September 21, 2012 12:13 PM
> To: Sebastien DELDON-GNB
> Cc: llvmdev at cs.uiuc.edu
> Subject: Re: RE : [LLVMdev] Question about LLVM NEON intrinsics
> On 21 September 2012 10:57, Sebastien DELDON-GNB
> <sebastien.deldon at st.com> wrote:
> > You're pointing me at ARM intrinsics related to loads, problem that I've
> reported in original e-mail, is not support for vector loads, but support for
> 'vmaxs'. For instance, there is no vector loads of 16 floats in ARM ISA but it is
> legal to write in LLVM:
> Oh, yes, sorry.
> Still, Eli is right, you can't assume generic IR will convert to platform-specific
> intrinsics automagically.
> This is not a bug, but could be a feature, if you want to write a NEON validator
> pass that pattern-matches generic LLVM IR operations into the respective
> (semantically correct) NEON intrinsics, or at least leave the IR operations in a
> state that the back-end will recognize it.
> Honestly, I prefer the approach to have the front-end writing generic IR and
> having target-specific passes that will change the generic IR to target specific,
> so the back-end can deal with it. But it seems that the front-ends had to deal
> with that, so far, including the ones I wrote. :/
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