[LLVMdev] Seperating registers in target description string replacement without adding whitespace?

ryan baird ryanrbaird at gmail.com
Fri Sep 14 07:25:03 PDT 2012

Here's an example piece of code to show you what I'm trying to do (on llvm

class ArithLogicR<bits<6> op, bits<6> func, string instr_asm, SDNode OpNode,
                  InstrItinClass itin, RegisterClass RC, bit isComm = 0>:
  FR<op, func, (outs RC:$rd), (ins RC:$rs, RC:$rt),
     !strconcat("+$rd=$rs ",!strconcat(instr_asm, " $rt")),
     [(set RC:$rd, (OpNode RC:$rs, RC:$rt))], itin> {
  let shamt = 0;
  let isCommutable = isComm;
  let isReMaterializable = 1;

This works, but I have to have the whitespace after $rs (which isn't
supported).  If I get rid of the space, I get a message like "ArithLogicR
doesn't have operand $rsAND" or something similar.  The point is that it
doesn't recognise $rs as a seperate entity.  Is there an encoding that it
supports seperating the registers from the operation without adding extra
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20120914/c0b759e3/attachment.html>

More information about the llvm-dev mailing list