[LLVMdev] Assert in LiveInterval update

[Jakob Stoklund Olesen]

On Sep 10, 2012, at 2:26 AM, Lang Hames <lhames at gmail.com> wrote:

> I've got a good test case that I'm working on at the moment. I noticed something odd though: Is '0' a valid register unit? I'm seeing a LiveInterval with li->reg == 0 show up, which previously wasn't valid. We have a few checks around the place to disregard the '0' physreg - could these trigger on interaction with a '0' interval? That could introduce some subtle bugs.

Right. Regunits are numbered independently from physregs, starting from 0. Each regunit corresponds to one or two physregs, the 'roots', which are typically leaf registers. The mapping is exposed by MCRegUnitIterator and MCRegUnitRootIterator.

Regunit live intervals are more strictly defined than the old physreg intervals. The same way a virtreg interval can be computed from all machine operands mentioning the virtreg, regunit intervals can be computed from all physreg operands with TRI->hasRegUnit(MO.getReg(), RegUnit).

However, while virtreg live intervals have a one-to-one mapping with machine operands, regunit intervals have a many-to-many mapping with the operands. A single physreg operand can affect multiple regunit intervals, and a regunit interval can be affected by different (overlapping) physregs.

It is best to avoid the MCRegUnitRootIterator+MCSuperRegIterator combination because the set of super-registers can be quite large on ARM.

/jakob