[LLVMdev] Unaligned vector memory access for ARM/NEON.

[Jim Grosbach]

VLD1 expects a 64-bit aligned address unless the target explicitly days that unaligned loads are OK.

For your situation, either the subtarget should set AllowsUnalignedMem to true (if that's accurate), or the load address should be made 64-bit aligned.

-Jim

On Sep 5, 2012, at 2:42 PM, Peter Couperus <peter.couperus at st.com> wrote:

> Hello all,
> 
> I am a first time writer here, but am a happy LLVM tinkerer.  It is a pleasure to use :).
> We have come across some sub-optimal behavior when LLVM lowers loads for vectors with small integers, i.e. load <4 x i16>* %a, align 2,
> using a sequence of scalar loads rather than a single vld1 on armv7 linux with NEON.
> Looking at the code in svn, it appears the ARM backend is capable of lowering these loads as desired, and will if we use an appropriate darwin triple.
> It appears this was actually enabled relatively recently.
> Seemingly, the case where the Subtarget has NEON available should be handled the same on Darwin and Linux.
> Is this true, or am I missing something?
> Do the regulars have an opinion on the best way to handle this?
> Thanks!
> 
> Pete
> 
> _______________________________________________
> LLVM Developers mailing list
> LLVMdev at cs.uiuc.edu         http://llvm.cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev