[LLVMdev] Data flow/liveness in register pairs

[Krzysztof Parzyszek]

Hello,

Consider this code (this is all after register allocation):

   R0<def> = ... R0    // Set lower half (based on the previous value)
   R1<def> = ...       // Set upper half
   ... = R0_R1         // Use the pair

It is my understanding that the use of the whole pair will need to have 
some sort of a reaching def, i.e. the code will need at least those flags:

   R0<def> = ... R0    // Set lower half (based on the previous value)
   R1<def> = ... R0_R1<imp-def>  // Set upper half (and the whole pair)
   ... = R0_R1         // Use the pair

The problem is that this will introduce data-flow dependency between the 
first and the second instruction, since the first one uses a half of 
what the second one implicitly defines.  What I want is to separate the 
information about a super-register being defined from the instructions 
that define parts of it.

I was contemplating something like this:
   R0<def> = ... R0    // Set lower half (based on the previous value)
   R1<def> = ...       // Set upper half
   R0_R1<def> = pseudo-consider-register-defined-here
   ... = R0_R1         // Use the pair
specifically with IMPLICIT_DEF, but that does not do what I thought it 
would.


I have also thought of doing this before register allocation, using 
something like this:
   vreg100:lower_half<def,read-undef> = ...
   vreg100:upper_half<def,read-undef> = ...
but the after the second instruction, the "lower_half" will revert to 
"undef" (at least according to my understanding).

Having simply
   vreg100:lower_half<def,read-undef> = ...
   vreg100:upper_half<def>            = ...
will treat the second instruction as an implicit use of both halves of 
vreg100 (and introduce the dreaded dependency).


Any suggestions as to how to deal with this?

-Krzysztof


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