[LLVMdev] Predication on SIMD architectures and LLVM

dag at cray.com dag at cray.com
Wed Oct 24 10:24:13 PDT 2012

David Chisnall <David.Chisnall at cl.cam.ac.uk> writes:

> I am talking about the LLVM select instruction, not a vector select:
> http://llvm.org/docs/LangRef.html#i_select

That is what I mean by a vector select.

> In any non-trapping case, an arithmetic operation (or sequence of
> operations) followed by a select is semantically equivalent to the
> predicated version.  


> Separating the select, which embodies the predication, from the
> operations allows more choice in terms of the final representation.


> Just because the generated machine code must contain predicated
> instructions most definitely does mean that the LLVM IR must contain
> it, or even that we would gain anything in terms of expressive power
> by permitting it.

Certainly such transformations *can* be done, but is it the most
efficient/best way to do things?  I wonder how many different passes of
"select to predication" we will end up having, one per target.


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