[LLVMdev] Alternate instruction encoding for subtargets

[Jaroslav Sýkora]

Hello,

I have a compiler in LLVM 2.9 for the KCPM3 processor. I'd like to
create a subtarget for the new cpu version called KCPSM6. Besides a
couple of new instructions which are not important at the moment, the
KCPSM6 cpu has different instruction opcodes. Semantically the
instructions are the same, hence I'd like to keep all the lowering and
pattern matching stuff unmodified

For example, the ADD sX, sY instruction in KCPSM3 is:
Inst{17-12} = 0b011000;
Inst{11-8} = sx;
Inst{7-4} = sy;
Inst{3-0} = 0;

While in KCPSM6 the same instruction is encoded:
Inst{17-12} = 0b010000;
Inst{11-8} = sx;
Inst{7-4} = sy;
Inst{3-0} = 0;

They even mostly kept the instruction formats!
Can I tell tablegen to have two encodings and switch between them
using a predicate?
I do not want to create new instructions (e.g. ADD_KCPSM3 and ADD_KCPSM6).
If that is not possible I will just dump the tablegen's
*GenCodeEmitter.inc file with the getBinaryCodeForInstr() and write it
by hand. I guess this is the only place where opcodes are used? (I do
not use LLVM's MC disassembler.)

Cheers,
Jara

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