[LLVMdev] X86 Tablegen Description and VEX.W

[Anitha Boyapati]

On 8 November 2012 20:59, Cameron McInally <cameron.mcinally at nyu.edu> wrote:
> On Thu, Nov 8, 2012 at 1:34 AM, Anitha Boyapati <anitha.boyapati at gmail.com>
> wrote:
> ...
>>
>> I actually have confusion in mapping the role of vex_w during
>>
>> instruction selection. For the moment, lets just consider vex_w and
>> not memop.
>>
>> [1]. What does " def rr : FMA4<>, VEX_W" mean? As per tablegen
>> description, "rr" now inherits FMA4 and VEX_W. However VEX_W is not a
>> class, it is an enumerated value.
>>
>
> VEX_W is a class, which sets the VEX.W bit to 1.
>
>> class VEX_W  { bit hasVEX_WPrefix = 1; }
>

Guess my grep from doxygen turned out to be outdated.

http://llvm.org/docs/doxygen/html/namespacellvm_1_1X86II.html

>> [3]. Why does only "rr" and "rm"  forms have vex_w but not "mr" ?
>
>
> In order to accept a memory address as the second source operand, the VEX.W
> bit must not be set. To accept a memory address as the third source operand,
> the VEX.W bit must be set. The VEX.W bit is of no consequence when all
> operands are from registers.

Thanks Cameron! That does sort out  everything.



- Anitha