[LLVMdev] load instruction memory operands value null

Fri Mar 30 01:50:31 PDT 2012

I felt I missed some additional information.

In the application, concerned pointer, 
UInt8 *ubNzCoeffChromaU;
is declared in .h and used/initialized in .c file.
 In a function, this is used as:
 for(j=0;j<2;j++)
 {
   if(j==0)
   {
     TmpNzCoeffChromaUV = ubNzCoeffChromaU;
     TmpChromaMacroblockUV = ChromaMacroblockU;
   }
   else
   {
     TmpNzCoeffChromaUV = ubNzCoeffChromaV;
     TmpChromaMacroblockUV = ChromaMacroblockV;
   }
 }We are processing single file using llc for multiple sources of application.

================
>>> (gdb) print MachInst->getParent()->dump()
BB#12: derived from LLVM BB %for.body40
Live Ins: %vr1 %vr2 %vr3 %vr4 %vr5 %vr6 %vr7 %vr8 %vr9 %vr10 %vr11
Predecessors according to CFG: BB#10 BB#11
DBG_VALUE %vr1, 0, !"CodedBlockPatternAll"; line no:1010
%vr12<def> = LD_Iri %vr2<kill>, 0; mem:LD4[<unknown>] dbg:workplace/src/SsvEntropy.c:1069:6
%vr13<def> = MOVr %vr6; dbg:workplace/src/SsvLibH264BpEntropyDecMB.c:1069:6
BNErr %vr3, %vr11, <BB#14>; dbg:workplace/src/SsvEntropy.c:1069:6
Successors according to CFG: BB#13 BB#14
$48 = void

>>> (gdb) print MachInst->getParent()->getPrev()->dump()
BB#11: derived from LLVM BB %for.body40
Live Ins: %vr1 %vr3 %vr4 %vr5 %vr6 %vr7 %vr8 %vr9 %vr10 %vr11
Predecessors according to CFG: BB#10
DBG_VALUE %vr1, 0, !"CodedBlockPatternAll"; line no:1010
%vr2<def> = MOVga <ga:@ubNzCoeffChromaU>; dbg:workplace/src/SsvEntropy.c:1071:7
Successors according to CFG: BB#12
$49 = void
--------------------- Definition of MOVga is -------------
def MOVga : InstXXX<(outs IntRegs:$dst), (ins i32imm:$src),
                      "mov_ga $dst, $src",
                      [(set IntRegs:$dst, (XXXMov tglobaladdr:$src))], Arith>;

-----------------------------------
the .ll referenced is:
for.body40:                                       ; preds = %for.inc250, %if.then32
  %j.023 = phi i32 [ %inc251, %for.inc250 ], [ 0, %if.then32 ]
 %12 = load i8** @ubNzCoeffChromaU, align 4, !dbg !1212
  tail call void @llvm.dbg.value(metadata !{i8* %12}, i64 0, metadata !1214), !dbg !1212
  tail call void @llvm.dbg.value(metadata !{i16* %add.ptr}, i64 0, metadata !1215), !dbg !1216
  %13 = load i8** @ubNzCoeffChromaV, align 4, !dbg !1217
  tail call void @llvm.dbg.value(metadata !{i8* %13}, i64 0, metadata !1214), !dbg !1217
  tail call void @llvm.dbg.value(metadata !{i16* %add.ptr2}, i64 0, metadata !1215), !dbg !1219
  %TmpNzCoeffChromaUV.0 = select i1 %cmp41, i8* %12, i8* %13, !dbg !1208
  %TmpChromaMacroblockUV.0 = select i1 %cmp41, i16* %add.ptr, i16* %add.ptr2, !dbg !1208

================
While analyzing, I found,
In file "lib/Target/X86/X86ISelLowering.cpp"
---------------------  MI creation --------------------
 MachineBasicBlock *MBB 
 MachineFunction *F = MBB->getParent();
 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();

 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) {
    int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;

    MachineMemOperand *MMO =
        F->getMachineMemOperand(
                           MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
                           MachineMemOperand::MOStore,
              /*Size=*/16, /*Align=*/16);
    BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
        .addFrameIndex(RegSaveFrameIndex)
       .addImm(/*Scale=*/1)
       .addReg(/*IndexReg=*/0)
       .addImm(/*Disp=*/Offset)
       .addReg(/*Segment=*/0)
       .addReg(MI->getOperand(i).getReg())
       .addMemOperand(MMO);
  }
==============================
I dumped, MI->getOperand(1)
(gdb) print MachInst->getOperand(1)
$50 = (const llvm::MachineOperand &) @0x93848fc: {OpKind = 0 '\000', SubReg = 0 '\000', TargetFlags = 0 '\000',
  IsDef = false, IsImp = false, IsKill = true, IsDead = false, IsUndef = false, IsEarlyClobber = false, IsDebug = false,
  SmallContents = {RegNo = 13, OffsetLo = 13}, ParentMI = 0x93e7868, Contents = {MBB = 0x93e63c0, CFP = 0x93e63c0,
    CI = 0x93e63c0, ImmVal = 667464718549410752, MD = 0x93e63c0, Sym = 0x93e63c0, Reg = {Prev = 0x93e63c0,
      Next = 0x9434fa0}, OffsetedInfo = {Val = {Index = 155083712, SymbolName = 0x93e63c0 "\374H8\t", GV = 0x93e63c0,
        BA = 0x93e63c0}, OffsetHi = 155406240}}}

where I see some garbage immediate value.

And for MI->getOperand(2)
(gdb) print MachInst->getOperand(2)
$52 = (const llvm::MachineOperand &) @0x9384910: {OpKind = 1 '\001', SubReg = 83 'S', TargetFlags = 0 '\000', IsDef = false,
  IsImp = false, IsKill = false, IsDead = true, IsUndef = false, IsEarlyClobber = false, IsDebug = false, SmallContents = {
    RegNo = 154502568, OffsetLo = 154502568}, ParentMI = 0x93e7868, Contents = {MBB = 0x0, CFP = 0x0, CI = 0x0, ImmVal = 0,
    MD = 0x0, Sym = 0x0, Reg = {Prev = 0x0, Next = 0x0}, OffsetedInfo = {Val = {Index = 0, SymbolName = 0x0, GV = 0x0,
        BA = 0x0}, OffsetHi = 0}}}

What I am concerned with is, is there a problem with SDNode creation or during MachineInstruction creation??

Thanks & Regards,
Pankaj

________________________________
From: Pankaj Gode <godepankaj at yahoo.com>
To: llvm Developers <llvmdev at cs.uiuc.edu> 
Sent: Friday, March 30, 2012 12:10 PM
Subject: [LLVMdev] load instruction memory operands value null

Hi,

For a custom target, there is a pass to perform memory dependence analysis, where, i need to get memory pointer for "load instruction". I want to check the pointer alias behavior. I am getting this by considering the memoperands for the load instruction. 

For "load instruction", Machine Instruction dumps as below:

vr12<def> = LD_Iri %vr2<kill>, 0; mem:LD4[<unknown>]

I checked for memoperands for this MachInst, which are not empty, as "has_empty()" returns false. When I check "Value *", pointed by memoperands_begin() and memoperands_end(), i get NULL value. Thus, I don't the the memory pointer.

What can be probable reasons for this behavior? or is this behavior expected? 

I have also checked in the lib/CodeGen/SelectionDAG/InstrEmitter.cpp, where MachineInstruction node is created from SDNode, but couldn't get much clue on this.

Thanks & Regards,
Pankaj

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