[LLVMdev] Expand vector type

[Duncan Sands]

Hi Javier,

On 05/03/12 18:10, Martinez, Javier E wrote:
> I still haven’t received any feedback on me adding support for widening of
> stores. Is there interest?

did you try LLVM 3.0?

Ciao, Duncan.

>
> Thanks,
>
> Javier
>
> *From:*llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] *On
> Behalf Of *Martinez, Javier E
> *Sent:* Wednesday, February 29, 2012 11:35 AM
> *To:* James Molloy; llvmdev at cs.uiuc.edu
> *Subject:* Re: [LLVMdev] Expand vector type
>
> James,
>
> Thanks for your response. I’m working in LLVM 2.7 (I know, it’s old) and the
> default behavior is already promote. This means that for example a call to
> DAGTypeLegalizer::getTypeAction(v3i32) in my case and I presume in ARM NEON
> returns TypeWidenVector. From here legalization calls WidenVectorOperand() to
> process the STORE node and follows the call chain I have on my original email to
> FindMemType().
>
> If my analysis is correct then your v316 STOREs are being broken into multiple
> ones depending on ARM NEON support. Can you please confirm?
>
> Thanks,
>
> Javier
>
> *From:*James Molloy [mailto:james.molloy at arm.com]
> <mailto:[mailto:james.molloy at arm.com]>
> *Sent:* Wednesday, February 29, 2012 2:35 AM
> *To:* Martinez, Javier E; llvmdev at cs.uiuc.edu <mailto:llvmdev at cs.uiuc.edu>
> *Subject:* RE: Expand vector type
>
> Hi,
>
> * *Is there a way to setup LLVM to automatically convert vec3s to vec4s? *
>
> **
>
> Yes, if you specify v3i16 and friends as “promote” instead of “legal”, llvm will
> promote it to a v4i16. The ARM NEON backend does this already. I’m surprised you
> haven’t got this happening already as you mention that LLVM widens your loads to
> 4-element vectors… (this should happen during DAG type legalization, by the way).
>
> Cheers,
>
> James
>
> *From:*llvmdev-bounces at cs.uiuc.edu <mailto:llvmdev-bounces at cs.uiuc.edu>
> [mailto:llvmdev-bounces at cs.uiuc.edu]
> <mailto:[mailto:llvmdev-bounces at cs.uiuc.edu]> *On Behalf Of *Martinez, Javier E
> *Sent:* 29 February 2012 00:27
> *To:* llvmdev at cs.uiuc.edu <mailto:llvmdev at cs.uiuc.edu>
> *Subject:* [LLVMdev] Expand vector type
>
> Hello,
>
> My input language has support for 3 and 4 element vectors but my target only has
> support for the latter. The language defines vec3 with the same storage space as
> vec4 so from a backend perspective they are both the same. I’d really like if I
> could have LLVM treat vec3 as vec4 but I haven’t found out how.
>
> Currently the target has emulated support for vec3 through LLVM. Loads are
> already widened by LLVM to a vec4. Stores are kind of funny. By default LLVM
> sets the action to ‘widen’ but in GenWidenVectorStores what ends up happening is
> an 2:1 split of the vector that’s less efficient in this case than actually
> widening the vector. The reason is that at this point the call to FindMemType
> assumes that stores can never be widened to a bigger type and so those types are
> not considered. The call sequence I’m looking at is WidenVectorOperand() ->
> WidenVecOp_STORE() -> GenWidenVectorStores() -> FindMemType(). I’ve made a very
> small modification to enable support for widening stores to a larger type.
>
> Before spending more time on working on a generic solution I have a couple of
> questions:
>
> * *Is there a way to setup LLVM to automatically convert vec3s to vec4s?*
>
> * *Is there interest in adding support for widened vector stores to a larger type?*
>
> Thanks,
>
> Javier
>
>
>
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