[LLVMdev] Aliasing bug or feature?

[Eli Friedman]

On Thu, Mar 1, 2012 at 1:04 PM, Sergei Larin <slarin at codeaurora.org> wrote:
> Hello everyone,
>
>  I am working on some changes to the Hexagon VLIW PreRA scheduler, and as a
> part of it need to test aliasing properties of two instruction.
> What it boils down to is the following code:
>
> char a[20];
> char s;
> char *p, *q; // p == &a[0]; q == &s;
>
> void test()
> {
>  register char reg;
>
>  s = 0;
>  reg = p[0] + p[1];
>  s = q[0] + reg;
>
>  return;
> }
>
> When I ask the question whether "&s" and "&q[0]" may potentially alias, I
> got negative affirmation.
> In the full test (not presented) they indeed may and do in fact alias,
> resulting in incorrect VLIW schedule.
>
> My question - is it a feature or a bug :)
>
> Here is somewhat more info:
>
> Before lowering begins:
> *** IR Dump After Remove sign extends ***
> define void @test() nounwind {
> entry:
>  store i8 0, i8* @s, align 1, !tbaa !0
>  %0 = load i8** @p, align 4, !tbaa !2
>  %1 = load i8* %0, align 1, !tbaa !0
>  %conv = zext i8 %1 to i32
>  %arrayidx1 = getelementptr inbounds i8* %0, i32 1
>  %2 = load i8* %arrayidx1, align 1, !tbaa !0
>  %conv2 = zext i8 %2 to i32
>  %3 = load i8** @q, align 4, !tbaa !2 <<< Can this load be bypassed by the
> store below?
>  %4 = load i8* %3, align 1, !tbaa !0
>  %conv5 = zext i8 %4 to i32
>  %add = add i32 %conv2, %conv
>  %add7 = add i32 %add, %conv5
>  %conv8 = trunc i32 %add7 to i8
>  store i8 %conv8, i8* @s, align 1, !tbaa !0 <<< Can this store bypass the
> above load?

Err, are you sure you're asking the right question?  Given the loads
you're pointing at, you're asking whether &s and &q alias.

-Eli