[LLVMdev] Back-end: how to test all lowering condition

[Christian Nastasi]

Dear All,
I am working on a back-end implementation for a new architecture which is provided with its own assembler.
I am currently capable of writing most of the lowering process to generate a decent assembly code.
Under certain circumstances, i.e. depending on the C code, some IR instructions generate a Selection DAG for which I am not implementing a proper lowering, thus resulting in the well-known "cannot select" error.
I guess this is because I have not implemented all possible instructions defined in the Selection DAG, those declared in include/llvm/CodeGen/ISDOpcodes.h, which apparently are different from those declared in the IR.

Problem1: how can I know the complete list of ISD:: instruction (SelectionDAG) I have to implement (either by promoting, customizing and expanding)?
A possible solution is to implement all of them, taking the list defined in the file mentioned above or taking the list from an already existing target (e.g. MSP430 Mips).

Problem2: even if I implement the complete list, how can I test it? I cannot write a .ll file containing directly the ISD:: instruction, but rather IR one that causes the former to appear in the SelectionDAG. In such case, what is the relationship between IR instructions and ISD:: ones?

Note to problem2: test/CodeGen/MSP430/setcc.ll is an example of test the uses the IR instruction "icmp" to generate the "setcc" SelectionDAG instruction.

Thank you all in advance for any suggestion you may give.
Cheers,
Christian.


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