[LLVMdev] Assert in live update from MI scheduler.

[Andrew Trick]

On Jun 13, 2012, at 10:49 AM, Sergei Larin <slarin at codeaurora.org> wrote:
> So if this early exit is taken:
> 
>  // SSA defs do not have output/anti dependencies.
>  // The current operand is a def, so we have at least one.
>  if (llvm::next(MRI.def_begin(Reg)) == MRI.def_end())
>    return;
> 
> we do not ever get to this point:
> 
>   VRegDefs.insert(VReg2SUnit(Reg, SU));
> 
> But later, when checking for anti dependency for another MI here:
> 
> void ScheduleDAGInstrs::addVRegUseDeps(SUnit *SU, unsigned OperIdx) {
> ...
>  // Add antidependence to the following def of the vreg it uses.
>  VReg2SUnitMap::iterator DefI = VRegDefs.find(Reg);
>  if (DefI != VRegDefs.end() && DefI->SU != SU)
>    DefI->SU->addPred(SDep(SU, SDep::Anti, 0, Reg));
> 
> We will never find that def in VRegDefs.find(Reg) even though it exists.
> 
> I know this has been working for a while, but I am still missing something
> here.
> What is this statement 
> 
> if (llvm::next(MRI.def_begin(Reg)) == MRI.def_end())
> 
> should guarantee? From it there must be more than one definition in MRI.def
> for that reg for it to work... 
> 
> 
> 
> 
> To connect it to the original example... When parsing (BU order) this
> instruction:
> 
> SU(1):   %vreg10<def> = LDriw %vreg9<kill>, 0; mem:LD4[%stack.0.in]
> 
> The %vreg10<def> never inserted to VRegDefs, so with next instruction:
> 
> SU(0):   %vreg1<def> = COPY %vreg10<kill>; IntRegs:%vreg1,%vreg10
> 
> Anti dep on %vreg10 is never created.


Thanks for the detailed explanation! My understanding is that COPY %vreg10<kill> is illegal because is has no reaching def on all paths (LDriw is the only def). 

Now, the (llvm::next(MRI.def_begin(Reg)) == MRI.def_end()) check is not really sufficient to test SSA in the presence of undefined operands. However, I thought we would have an IMPLICIT_DEF of the vreg in that case, even after the phi is removed. That right Jakob? Otherwise we I think we should somehow mark the vreg as being undefined.

Anyway, I added an assert to catch this problem (see below), and it never triggered on X86. So my guess is that you have incorrect IR coming in. Can you check where %vreg10 is defined. Before coalescing, was it a phi with an <undef> operand?

It is safe to workaround the problem by removing the early exit following the SSA check.

-Andy

--- a/lib/CodeGen/ScheduleDAGInstrs.cpp
+++ b/lib/CodeGen/ScheduleDAGInstrs.cpp
@@ -413,9 +413,11 @@ void ScheduleDAGInstrs::addVRegDefDeps(SUnit *SU, unsigned OperIdx) {
 
   // SSA defs do not have output/anti dependencies.
   // The current operand is a def, so we have at least one.
-  if (llvm::next(MRI.def_begin(Reg)) == MRI.def_end())
+  if (llvm::next(MRI.def_begin(Reg)) == MRI.def_end()) {
+    //!!!
+    VRegDefs.insert(VReg2SUnit(Reg, SU));
     return;
-
+  }
   // Add output dependence to the next nearest def of this vreg.
   //
   // Unless this definition is dead, the output dependence should be
@@ -479,8 +481,10 @@ void ScheduleDAGInstrs::addVRegUseDeps(SUnit *SU, unsigned OperIdx) {
 
   // Add antidependence to the following def of the vreg it uses.
   VReg2SUnitMap::iterator DefI = VRegDefs.find(Reg);
-  if (DefI != VRegDefs.end() && DefI->SU != SU)
+  if (DefI != VRegDefs.end() && DefI->SU != SU) {
+    assert(llvm::next(MRI.def_begin(Reg)) != MRI.def_end() && "SINGLEDEF");
     DefI->SU->addPred(SDep(SU, SDep::Anti, 0, Reg));
+  }

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