[LLVMdev] Instruction bundles before RA: Rematerialization

[Ivan Llopard]

Hi,

We have a new BE for a VLIW-like processor and I'm currently working on 
instruction bundles. Ideally, I'd like to have bundles *before* RA to 
model certain constraints, e.g. the exposed one by Tzu-Chien a while ago 
in his thread 
http://lists.cs.uiuc.edu/pipermail/llvmdev/2005-September/004798.html

In order to build bundles, we have added a new bottom-up MIScheduler, 
right after reg coalescing, which behaves much like ScheduleDAGVLIW but 
without hazard recognizing. Due to some tricky instructions, we cannot 
schedule on the DAG. Bundles are built at exitRegion() in the scheduling 
process and the live interval information is updated correctly. After 
this, the RA is aware of bundles, at least from a LiveInterval point of 
view, and I had some problems regarding the rematerialization.

AFAIK, the RA cannot remat if the target instruction is not the bundle's 
header.
For this, I rather need a light bundle representation, or no bundle at 
all, so it can remat the right instruction with one condition: the 
remated location should preserve bundles. Nevertheless, for many other 
actions like LI splitting, the current representation works very well.

In general, I want the RA to preserve bundles as well as to be able to 
model the constraint presented above in the thread.
Should I fix the rematerialization code to look for the right 
instruction into the current bundle ?
What's the direction you are following about instruction bundling ?

We would like to follow llvm evolutions and preserve the core 
implementations as much as possible.

Thanks in advance,

Ivan