[LLVMdev] Predicate registers/condition codes question

[Duncan Sands]

Hi,

>> The problem is that the existing integer arithmetic operations on i8
>> are not legal to be executed on the predicate registers (i.e., clang
>> would generate an i8 expression for the addition of two char
>> variables.)  Hexagon cannot do integer arithmetic operations using the
>> predicate registers.

so what can you actually do with predicate registers?

Ciao, Duncan.

   The addition of two char variables has to be
>> promoted to the next available integer arithmetic register: that is
>> i32.  Because LLVM automatically legalizes i8 types, it considers all
>> operations to be legal on i8 (i.e., both integer and boolean arithmetic.)
>>
>> So the solution that I was investigating looks like this:
>>
>>       for (unsigned int i = 0; i<   ISD::BUILTIN_OP_END; ++i) {
>>         switch (i) {
>>         // By default all operations on i8 have to be promoted to i32.
>>         default:
>>           setOperationAction(i, MVT::i8, Custom);
>>           break;
>>
>>         // Only the following operations are legal on i8 predicates.
>>         case ISD::AND:
>>         case ISD::OR:
>>         case ISD::XOR:
>>         case ISD::SETCC:
>>         case ISD::SIGN_EXTEND:
>>          break;
>>         }
>>       }
>>
>> and promote all i8 to i32 in HexagonTargetLowering::LowerOperation
>
> That's hard work! Why don't you call it with "Promote" instead of
> "Custom" and let the Legalizer do the job? Does it not work?
>
>
> Ivan
>
>>
>>> default. The latter will require a little hack though...
>>> I hope this helps.
>>
>> Thanks again for your ideas and guidance: very much appreciated.
>>
>> Sebastian
>> --
>> Qualcomm Innovation Center, Inc is a member of Code Aurora Forum
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