[LLVMdev] VLIW code generation for LLVM backend

[Triple Yang]

Hi,

It seems the only one VLIW target Hexagon in LLVM 3.2 devel uses a
straightforward way to emit its VLIW-style asm codes.
It uses a list scheduler to schedule on DAG and a simple packetizer to
wrap the emitted asm instructions.
Both scheduling and packetizing work on basic blocks.

so, is there any plan to implement better optimization methods such as
trace scheduling, software pipelining, ...
or  is it already going on?

Best regards.

-- 
杨勇勇 (Yang Yongyong)