[LLVMdev] Bind a LLVM variable to a CPU register

Xin Tong xerox.time.tech at gmail.com
Thu Jul 19 13:00:34 PDT 2012


On Thu, Jul 19, 2012 at 3:54 PM, Xin Tong <xerox.time.tech at gmail.com> wrote:
> On Thu, Jul 19, 2012 at 2:28 PM, John Criswell <criswell at illinois.edu> wrote:
>> On 7/19/12 1:23 PM, Jim Grosbach wrote:
>>>
>>> Not really, no.
>>
>>
>> If you really, really, wanted to do it, you could:
>>
>> 1) Hack the code generator to not use that register.  It might be as simple
>> as modifying the TableGen file to not know that the register exists.
>
> In fact this is what i am thinking at this point. but i want to keep
> the modification to the LLVM as little as possible. There is no
> existing APIs to disable the use a machine register, is there ?

or is there a way i can stick a register dependence ( pre-instruction
dependence and/or post-instruction dependence ) on a LLVM IR node
before i sent it to the codegenerator.

>
>> 2) Use inline asm to put the constant into that register and fetch it from
>> that register.
>>
>> The real question is: what larger goal are you trying to accomplish?
>> Holding a constant value in a register might not be the best way to do what
>> you're doing.
>>
>> -- John T.
>>
>>
>>>
>>> On Jul 19, 2012, at 11:14 AM, Xin Tong <xerox.time.tech at gmail.com> wrote:
>>>
>>>> I have a constant parameter in a LLVM function. Is there a way to
>>>> reserve a CPU register such that it also holds the value of the
>>>> parameter in LLVM x86 codegen ?
>>>>
>>>> Thanks
>>>>
>>>> Xin
>>>> _______________________________________________
>>>> LLVM Developers mailing list
>>>> LLVMdev at cs.uiuc.edu         http://llvm.cs.uiuc.edu
>>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev
>>>
>>> _______________________________________________
>>> LLVM Developers mailing list
>>> LLVMdev at cs.uiuc.edu         http://llvm.cs.uiuc.edu
>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev
>>
>>



More information about the llvm-dev mailing list