[LLVMdev] Tablegen: How to define a Pattern with multiple result instructions

[Jim Grosbach]

TableGen can do this if the second instruction uses the result of the first as an input, but not if they're completely separate like this. The output pattern must be in the form of a DAG.

You probably want to do this via a custom lowering and/or pseudo instructions that get expanded after isle.

-Jim

On Jan 19, 2012, at 4:21 PM, Tom Stellard wrote:

> Hi,
> 
> I'm trying to create a Pattern that looks something like this:
> 
> def my_inst : Instruction <
>  let OutOperandList = (outs REG:$dst);
>  let InOperandList = (ins imm:$src);
>  let Uses = [R0];
>> 
> 
> def int_my_intrinsic : Intrinsic < 
>  [llvm_float_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []
>> ;
> 
> def : Pattern <
>  (int_my_intrinsic imm:$a, imm:$b, imm:$c),
>  [(set R0, (MOV_IMM imm:$a)),
>   (my_inst (my_inst $b), $c)]
>> ;
> 
> When I try to run this through tablegen, I get this error:
> "Cannot handle instructions producing instructions with temporaries
> yet!"
> 
> What does this error message mean? Is what I'm trying to do even
> possible with tablegen?
> 
> Thanks,
> Tom
> 
> 
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