[LLVMdev] Pattern matching in a SelectionDAG

[dodo]

The graph of your second instruction looks like this:


  $dst <-----      +
                       /   \
                      /     \
                   $b    $c

No set in BA instruction pattern because no dest register should be updated.
in ADD instruction pattern, you should update your dest register $dst with
the value (add IntRegs:$b, IntRegs:$c).


On 18 January 2012 10:36, Matthias Berndt <
matthias.berndt at studserv.uni-leipzig.de> wrote:

> Hi,
>
> I'm trying to write an LLVM backend using LLVM's retargetable code
> generator, and I'm confused about how the SelectionDAG works. Let me give
> you an example from the SPARC backend (as this is what is often mentioned
> in the documentation). This is how the "branch always" instruction is
> defined:
>
> def BA   : BranchSP<0b1000, (ins brtarget:$dst),
>                      "ba $dst",
>                      [(br bb:$dst)]>;
>
> The pattern that is to be matched is simply (br bb: $dst). Based on this, I
> would have expected the pattern for an add instruction to look somehow like
> this: (add IntRegs:$b, IntRegs:$c). But in reality, it looks like this:
> (set IntRegs:$dst, (add IntRegs:$b, IntRegs:$c))
> What is this "set" thing all about? It doesn't seem to be a node in the
> graph, as the pattern is also matched in a graph in which the add node's
> ancestor is, say, a mul node. So what is it?
>
> Cheers
> Matthias
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>



-- 
Sincerely,

Aries Wu
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