[LLVMdev] PTX backend fails instruction selection for load of sext

[Jonathan Ragan-Kelley]

Loads (on ptx64) with an sext of a computed index operand fail instruction selection:

LLVM ERROR: Cannot select: 0x7ff01401c210: i64,ch = load 0x10580e820, 0x7ff01401b510, 0x7ff01401b910<LD4[%memref1], sext from i32> [ID=8]
  0x7ff01401b510: i64 = PTXISD::LOAD_PARAM 0x10580e820, 0x7ff01401b410 [ORD=2] [ID=6]
  0x7ff01401b910: i64 = undef [ORD=4] [ID=3]

This is for code of the form:

  %ptr = gep i64* %base, i32 %offset
  %v = load i64* %ptr

when the offset gets directly inlined into the selection DAG slot of the load during lowering. If it's managed to be stored off in a vreg or something first (like if it's common subexpression eliminated with another sext of the same value to i64 that gets used before), this doesn't happen and codegen works fine.

The attached trivial ll fails with llc -march=ptx64, and works if either of the "works" paths is uncommented instead of "breaks".

Any suggestions for where to look would be hugely appreciated. This has crept out from the closed just in time to bite me before a major paper deadline on Tuesday.

Thanks.

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