[LLVMdev] ARMLoadStoreOptimizer bug

[David Meyer]

Anton,

I'm afraid I really can't produce a meaningful example. The bug is
extremely sensitive to code placement, optimization. I had to do a terrible
amount of drugdery to find it in the first place.

Here's how I found the bug:

1) Stage 1: Compile LLVM with build/host x86, target ARM.
2) Stage 2: Cross-compile LLVM with host ARM, target ARM, using the stage 1
Clang/LLVM.
3) Use the stage 2 LLVM (in an ARM emulator) to compile an application, Foo.
4) Run Foo.
5) Foo malfunctions.

To find the bug, I had to do the following:

1) Notice that Foo does not malfunction when compiled using the stage 1
LLVM.
2) Diff between Foo.s generated by stage 1 LLVM and stage 2 LLVM. This made
it obvious which instructions in Foo.s were causing the malfunction.
3) Determine why the stage 2 LLVM produced those instructions, instead of
the correct ones.
5) Find the instructions (in the LLVM stage 2 executable) which are causing
the incorrect behavior.
6) Determine why the stage 1 LLVM emitted these instructions, instead of
the correct ones.

My search ended at the ARM Load/Store rewrite pass. By scanning the debug
output by hand, I determined that the bad code appeared during this pass.
After I disabled this pass, all bugs in the stage 2 build went away.

Although, I can't produce a reasonable example, I think it should be
obvious based on the debug output I gave above what is wrong. I did a quick
review of the code in the ARM Load/store pass, and it seems to never take
into account the liveness state of CPSR after ADDri. Please let me know if
I'm mistaken in this assessment.

Thanks,
- pdox


On Sun, Feb 5, 2012 at 2:15 PM, Anton Korobeynikov
<anton at korobeynikov.info>wrote:

> Hello David,
>
> > I'm seeing a case where ARM Load/Store optimizer is breaking code. I have
> > not had any luck trying to come up with a minimal example; it is
> breaking in
> > our stage 2 LLVM build.
> Still, *any* testcase is better than no testcase :)
>
> --
> With best regards, Anton Korobeynikov
> Faculty of Mathematics and Mechanics, Saint Petersburg State University
>
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