[LLVMdev] CodeGen instructions and patterns
محمد ﻋﻤﺮ ﺩﻫﻠﻮﻯ
omerbeg at gmail.com
Fri Feb 24 11:47:23 PST 2012
> > otherwise how are the machine instructions being accessed/matched for
> instruction selection ?
> Have a look at the code in SelectionDAGISel.
I am looking at the ARM backend.
In specific, the instruction selection.
In Select(N), I only see ad-hoc matches on the basis of the opcode in the
provided SDNode of the DAG, and then getMachineNode() is being used to
generate the machine instruction.
Am I understanding this correctly ?
Consider the following multiply add insstruction, given in ARMInstrInfo.td
def MLA : AsMul1I32<0b0000001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm,
IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra",
[(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))]>
How do I get this instruction and it corresponding pattern in the selector ?
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