[LLVMdev] DAG optimization and lowering algorithm

Demikhovsky, Elena elena.demikhovsky at intel.com
Tue Feb 7 01:11:25 PST 2012

One of possible solutions is running Combine() for full DAG cycle after cycle while anything is changed.

And remember that if we plan to optimize something after type legalization and before operation legalization
if (DCI.isBeforeLegalizeOps()) && !DCI.isBeforeLegalize()) {

The function may not be called at all.

- Elena

-----Original Message-----
From: Eli Friedman [mailto:eli.friedman at gmail.com] 
Sent: Tuesday, February 07, 2012 10:58
To: Demikhovsky, Elena
Cc: llvmdev at cs.uiuc.edu
Subject: Re: [LLVMdev] DAG optimization and lowering algorithm

On Tue, Feb 7, 2012 at 12:38 AM, Demikhovsky, Elena
<elena.demikhovsky at intel.com> wrote:
> At the beginning, I have the following chain: LOAD -> TRUNCATE -> ZERO_EXTEND.
> After Combine(BeforeLegalizeTypes) the optimization of ZERO_EXTEND  gives me the new chain LOAD -> ANY_EXTEND -> AND.
> I want to optimize ANY_EXTEND but is not analyzed in the same Combine().

That sounds like it's just a matter of making sure we don't forget to
add the ANY_EXTEND to the worklist.  We don't need a whole additional
DAGCombine run for that.

Intel Israel (74) Limited

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