[LLVMdev] ARMLoadStoreOptimizer bug

[David Meyer]

Evan & llvmdev,

I'm seeing a case where ARM Load/Store optimizer is breaking code. I have
not had any luck trying to come up with a minimal example; it is breaking
in our stage 2 LLVM build.

But here's what I'm seeing in the debug output:

# Before ARMLoadStoreOptimizer:
BB#21: derived from LLVM BB %cond.end
    Live Ins: %LR %R0 %R1 %R7 %R10 %R11
    Predecessors according to CFG: BB#14 BB#18
        STRi12 %R7<kill>, %R1, 0, pred:14, pred:%noreg;
mem:ST4[%first257](tbaa=!"int")
        %R1<def> = ADDri %R1<kill>, 4, pred:14, pred:%noreg, opt:%CPSR<def>
        Bcc <BB#23>, pred:0, pred:%CPSR<kill>
        B <BB#22>
    Successors according to CFG: BB#23 BB#22

# After ARMLoadStoreOptimizer:
BB#21: derived from LLVM BB %cond.end
    Live Ins: %LR %R0 %R1 %R7 %R10 %R11
    Predecessors according to CFG: BB#14 BB#18
        %R1<def> = STR_POST_IMM %R7<kill>, %R1, %noreg, 4, pred:14,
pred:%noreg
        Bcc <BB#23>, pred:0, pred:%CPSR<kill>
        B <BB#22>
    Successors according to CFG: BB#23 BB#22

It appears that the ARM Load/Store optimizer has rolled the ADDri and
STRi12 into the STR_POST_IMM, but has ignored the fact that ADDri sets CPSR
(which is used by the following Bcc), whereas STR_POST_IMM does not set
CPSR.

- pdox
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