[LLVMdev] Increase the number of registers in ARM

陳韋任 (Wei-Ren Chen) chenwj at iis.sinica.edu.tw
Thu Dec 6 17:27:01 PST 2012

On Thu, Dec 06, 2012 at 09:13:53AM +0000, David Chisnall wrote:
> On 6 Dec 2012, at 07:46, 陳韋任 (Wei-Ren Chen) wrote:
> >  The code below in lib/Target/ARM/ARMRegisterInfo.td is where you
> > should look into,
> > 
> > // Integer registers
> > def R0  : ARMReg< 0, "r0">,  DwarfRegNum<[0]>;
> > def R1  : ARMReg< 1, "r1">,  DwarfRegNum<[1]>;
> > 
> >  ...
> That's the easy part.  ARM (AArch32) has 16 registers because register operands are stored in a 4-bit bitfield in the instructions.  If you want to add more registers, then you will also need to modify the instruction encoding of every instruction, or place them in a separate namespace (as with the NEON / VFP registers) and add instructions for explicitly modifying them.

  Oh, I miss that part. So since the ARM only save 4 bits for register
operand, I don't see there is a easy way to do what you said. Sounds
like a huge work?

Wei-Ren Chen (陳韋任)
Computer Systems Lab, Institute of Information Science,
Academia Sinica, Taiwan (R.O.C.)
Tel:886-2-2788-3799 #1667
Homepage: http://people.cs.nctu.edu.tw/~chenwj

More information about the llvm-dev mailing list