[LLVMdev] No more TargetFlags on MO_Register MachineOperands

[Owen Anderson]

On Aug 22, 2012, at 11:52 AM, "Villmow, Micah" <Micah.Villmow at amd.com> wrote:

> 
> 
>> -----Original Message-----
>> From: Owen Anderson [mailto:resistor at mac.com]
>> Sent: Wednesday, August 22, 2012 11:41 AM
>> To: Villmow, Micah
>> Cc: Stellard, Thomas; llvmdev at cs.illinois.edu
>> Subject: Re: [LLVMdev] No more TargetFlags on MO_Register
>> MachineOperands
>> 
>> Not particularly.  There are backends already in existence that make
>> heavy use of it.  The key is that def : Pat constructs can take
>> advantage of all of the same mechanisms for factoring out commonality
>> that normal patterns can, including multiclasses and ComplexOperands.
> [Villmow, Micah] Can you provide example of it having to occur everywhere? The instruction enum list for my backend 6867 enums long and growing. Now the proposed solution is I have to write a pattern/duplicate every single instruction so I can add a literal operand for every register operand and an extra for every instruction. Instead of just providing 8-16 bits of information that the backend can do whatever it wants with, which seems like a much cleaner and simpler solution.

One way around this is to use a ComplexOperand to represent the combination of the register+immediate.  A ComplexOperand is selected via a C++ callback, which has the liberty of doing things like providing a default value for any of its subcomponents.

Tom's idea regarding adding a new tblgen construct for a default-valued immediate is also interesting, though it might be tricky to get it to interact properly with things like the AsmParser.

--Owen