[LLVMdev] More Back-End Porting Troubles

[Tom Stellard]

On Wed, Aug 15, 2012 at 06:11:52PM +0200, Fabian Scheler wrote:
> Hi LLVM-Folks,
> 
> as mentioned in an earlier post
> (http://lists.cs.uiuc.edu/pipermail/llvmdev/2012-July/051677.html) I
> am currently working on a Back-End for the TriCore processor.
> Currently, I am struggling as LLVM could not select zext and load, for
> instance, so some of the testcases in test/CodeGen/Generic are not
> successfully compiled by my back-end.
> Furthermore, I am completely puzzled by the error messages generated.
> The testcase 'test/CodeGen/Generic/pr12507.ll' for instance yields:
> 
> LLVM ERROR: Cannot select: 0x229dbd0: i64,ch = load 0x226ee70,
> 0x229d8d0, 0x229d9d0<LD4[FixedStack-1](align=8), zext from i32>
> [ID=14]
>   0x229d8d0: i64 = FrameIndex<-1> [ORD=1] [ID=3]
>   0x229d9d0: i64 = undef [ORD=1] [ID=4]
> 
> What exactly does this mean? OK, it means that some load instruction
> could not be selected. But why? Is the instruction not supported as it
> is (I doubt this as there are such instructions defined according with
> appropriate patterns)? Is the addressing mode node supported (how
> could I derive this information)? Is there a way how I can extract
> that information from these error messages in an "easy" manner?
>

If you run llc with -debug-only=isel, it will dump the decision process
for the lowering of each instruction.  The index numbers in that dump
refer to predicates in TriCoreGenDAGISel.inc.  This should help you
figure out why it isn't being selected.

-Tom