[LLVMdev] Load serialisation during selection DAG building

[Dan Gohman]

On Aug 14, 2012, at 2:05 PM, Steve Montgomery <stephen.montgomery3 at btinternet.com> wrote:

> Further to my earlier question, I'm perhaps a bit confused about memory serialisation. The following example, compiled using clang for the MSP430:
> 
> target datalayout = "e-p:16:16:16-i8:8:8-i16:16:16-i32:16:32-n8:16"
> target triple = "msp430-??-??"
> 
> @y = common global i16 0, align 2
> @x = common global i16 0, align 2
> 
> define void @f() nounwind {
> entry:
>   %0 = load i16* @y, align 2, !tbaa !0
>   %1 = load volatile i16* @x, align 2, !tbaa !0
>   %add = add i16 %1, %0
>   store i16 %add, i16* @y, align 2, !tbaa !0
>   ret void
> }
> 
> has a chain store->load volatile->load. I thought this meant that the load volatile had to occur _after_ the load but the MSP430 backend selects the ADD16mm instruction for which I suspect the order of operand access isn't specified. So, does the chain mean "no earlier than" rather than "later than"?

No, a chain is supposed to mean "later than". It sounds like MSP430 is bending
the rules here.

Dan