[LLVMdev] The use-define chain in LLVM

[Jianfei Hu]

Maybe My statement is not clear. Take an example:
main.c:
int global;
void fun(int array[], int i){
	array[i] = i + 1;
        global = i;
}

int main(){
	int arr[40], i = 0;
	fun(arr, 10);
	return 0;
}
Can I determine whether the value of arr array and global variable
have changed after the function call, fun(arr, 10), by LLVM API? It
could be more complicated considerring the nested function call, and
variable pointer alias. Does LLVM offer the interface to solve that?

2012/8/9 Alex Rønne Petersen <xtzgzorex at gmail.com>:
> On Thu, Aug 9, 2012 at 6:57 AM, Jianfei Hu <hujianfei258 at gmail.com> wrote:
>> Thanks for your response!
>>
>> But I want to determine wheter the specific variable's value has been
>> changed between
>> two usages of variable, and wheter the parameter's value is changed in
>> a function. Like the
>> reaching definition analysis, and ud chains.
>>
>>
>> 2012/8/9 陳韋任 (Wei-Ren Chen) <chenwj at iis.sinica.edu.tw>:
>>> On Thu, Aug 09, 2012 at 11:16:15AM +0800, Jianfei Hu wrote:
>>>> Hello All,
>>>>
>>>>         Is the use-define chain related API avaliable in LLVM? I want
>>>> to get the information
>>>> about the variables' value changes at different points in the program.
>>>
>>>   Is this [1] fit your need?
>>>
>>> HTH,
>>> chenwj
>>>
>>> [1] http://llvm.org/docs/ProgrammersManual.html#iterate_chains
>>
>> This just supplys the variables used by the one instruction.
>> Is there any other class/API that can meet my demands?
>> Or I have to implement it by myself from the llvm IR code?
>>
>>>
>>> --
>>> Wei-Ren Chen (陳韋任)
>>> Computer Systems Lab, Institute of Information Science,
>>> Academia Sinica, Taiwan (R.O.C.)
>>> Tel:886-2-2788-3799 #1667
>>> Homepage: http://people.cs.nctu.edu.tw/~chenwj
>>
>>
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>>
>
> I don't know how low-level you plan to work at, but at the LLVM IR
Do you mean the LLVM could generate a higher level representative,
instead of IR, like AST? I just know the IR code level.

> level, a register can only be defined once (LLVM IR is in SSA form),
> so while a register can have multiple uses, it can only have one
> definition (or none, in the case of registers that aren't
> initialized).
>
> Regards,
> Alex