[LLVMdev] Tablegen foreach

[Jim Grosbach]

On Aug 6, 2012, at 3:13 PM, Sean Silva <silvas at purdue.edu> wrote:

> I believe multiclasses can be nested. Could that help you reduce the
> duplication?

Yes they can. I believe X86 does so, for example.

-Jim

> 
> --Sean Silva
> 
> On Mon, Aug 6, 2012 at 2:46 PM, Villmow, Micah <Micah.Villmow at amd.com> wrote:
>> That is what I currently have, I'm trying to simplify them even further since my multiclass file is enormous because of the amount of combinations. I have things like this:
>> 
>> multiclass instmcRegImm<...> {
>> def rr: inst<...>;
>> def ri: inst<...>;
>> def ir: inst<...>;
>> def ii: inst<...>;
>> }
>> multiclass instmc<...> {
>> defm i8 : instmcRegImm<...>;
>> ^-- repeat for 15 more register classes.
>> }
>> defm INST : instMC<..>;
>> 
>> Then I need to repeat this for SDNodes, PatFrags, Intrinsics, etc... This doesn't even take into account special case instructions. I know that Owen's work on overloaded nodes will help here, but even then, it is just a lot of duplicate code.
>> 
>> Micah
>> 
>>> -----Original Message-----
>>> From: Sean Silva [mailto:silvas at purdue.edu]
>>> Sent: Monday, August 06, 2012 2:37 PM
>>> To: Villmow, Micah
>>> Cc: llvmdev at cs.uiuc.edu (LLVMdev at cs.uiuc.edu)
>>> Subject: Re: [LLVMdev] Tablegen foreach
>>> 
>>> I think a multiclass may be a better fit for what you are trying to
>>> do. In fact, this is the canonical example for multiclasses:
>>> <http://llvm.org/docs/TableGenFundamentals.html#multiclass-definitions-
>>> and-instances>.
>>> 
>>> --Sean Silva
>>> 
>>> On Mon, Aug 6, 2012 at 1:55 PM, Villmow, Micah <Micah.Villmow at amd.com>
>>> wrote:
>>>> I'm trying to find examples of the foreach pattern being used in
>>> tablegen
>>>> files.
>>>> 
>>>> The problem I am trying to solve is to simplify the amount of
>>> tablegen code
>>>> I have to produce because each operand of an instruction can be a
>>> register
>>>> or a literal.
>>>> 
>>>> So for binary, we have 4 instructions, ternary, 8, and quaternary 16
>>>> combinations.
>>>> 
>>>> 
>>>> 
>>>> Instead of writing all the combinations out, I'd like to use nested
>>> foreach
>>>> loops to generate, the problem I'm having is that I cannot seem to
>>>> conditionally set a DAG node on the foreach variable.
>>>> 
>>>> 
>>>> 
>>>> For example:
>>>> 
>>>> foreach a in ["r", "I"] in {
>>>> 
>>>> def ADD#a : Inst<!if(!eq(#a, "r"), i32Reg, i32imm)>;
>>>> 
>>>> }
>>>> 
>>>> 
>>>> 
>>>> So, is this possible? It seems to be no to me. What could be another
>>> way of
>>>> doing this without having massive code duplication.
>>>> 
>>>> 
>>>> 
>>>> Thanks,
>>>> 
>>>> Micah
>>>> 
>>>> 
>>>> _______________________________________________
>>>> LLVM Developers mailing list
>>>> LLVMdev at cs.uiuc.edu         http://llvm.cs.uiuc.edu
>>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev
>>>> 
>> 
>> 
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