[LLVMdev] Tablegen foreach

[Villmow, Micah]

I'm trying to find examples of the foreach pattern being used in tablegen files.
The problem I am trying to solve is to simplify the amount of tablegen code I have to produce because each operand of an instruction can be a register or a literal.
So for binary, we have 4 instructions, ternary, 8, and quaternary 16 combinations.

Instead of writing all the combinations out, I'd like to use nested foreach loops to generate, the problem I'm having is that I cannot seem to conditionally set a DAG node on the foreach variable.

For example:
foreach a in ["r", "I"] in {
def ADD#a : Inst<!if(!eq(#a, "r"), i32Reg, i32imm)>;
}

So, is this possible? It seems to be no to me. What could be another way of doing this without having massive code duplication.

Thanks,
Micah
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