[LLVMdev] Register Coalescer does not preserve TargetFlag

[Vincent Lejeune]

Do you know any backend that implement instructions as a flag modifier in instruction ?

Thank,
Vincent Lejeune



----- Mail original -----
> De : Jakob Stoklund Olesen <stoklund at 2pi.dk>
> À : Vincent Lejeune <vljn at ovi.com>
> Cc : "llvmdev at cs.uiuc.edu (LLVMdev at cs.uiuc.edu)" <llvmdev at cs.uiuc.edu>
> Envoyé le : Lundi 6 août 2012 20h06
> Objet : Re: [LLVMdev] Register Coalescer does not preserve TargetFlag
> 
> 
> On Aug 6, 2012, at 11:00 AM, Vincent Lejeune <vljn at ovi.com> wrote:
> 
>>  Ok.
>> 
>>  I tried to do it using a pass after register allocation, lowering NEG/ABS 
> instructions.
>>  However I met a problem : apparently getNextOperandForReg() can returns a 
> MachineOperand before the one I'm processing.
>> 
>>  The following code snippet : 
>> 
>> 
>>  void R600ModifiersPropagation::substituteReg(MachineOperand &def_MO, 
> unsigned new_reg, unsigned char flag) {
>>    MachineOperand * MO = def_MO.getNextOperandForReg();
>>    while (MO && MO->isUse()) {
>>      MachineOperand *next_MO = MO->getNextOperandForReg();
>>      MO->dump();
>> 
>>      MO = next_MO;
>>    }
>>  }
>> 
>>  displays instructions that are before the one I'm passing as def_MO. 
> I'm not sure if I should call some Analysis pass to enforce MachineOperand 
> order or not.
> 
> We make no guarantees about the order of operands in the use-def chains, and 
> there are no analyses that can reorder them.
> 
> I would suggest that you read the code in other targets to see how things are 
> usually done.
> 
> /jakob
>