[LLVMdev] TableGen related question for the Hexagon backend

[Sebastian Pop]

On Thu, Aug 2, 2012 at 5:23 PM, Jakob Stoklund Olesen <stoklund at 2pi.dk> wrote:
> The problem is, this isn't really any better than having a large switch statement. You just moved the table into the .td file.
>
> You should be taking advantage of the instruction multiclasses so you don't have to maintain a full table of opcodes.

We wouldn't need to "maintain" this table of opcodes, as this table is
extracted from a higher level representation of the instruction set.
In particular, this table would not need to be modified at all for the
existing supported processors, and any new version of processors will
have its table automatically generated by us.

Why wouldn't it be acceptable for the *.td files defining the instructions
and the relations between them to be generated and not written by hand?

In my opinion, generating parts of the td files is much less error prone and
more convenient for us than having to write the insns definitions by hand
(that would indeed need "maintenance".)

Thanks,
Sebastian
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