[LLVMdev] MemRefs in a Load Instruction

[Pranav Bhandarkar]

> -----Original Message-----
> From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu]
> On Behalf Of Pranav Bhandarkar
> Sent: Thursday, April 26, 2012 8:01 PM
> To: llvmdev at cs.uiuc.edu
> Subject: Re: [LLVMdev] MemRefs in a Load Instruction
> 
> 
> 
> > -----Original Message-----
> > From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-
> bounces at cs.uiuc.edu]
> > On Behalf Of Pranav Bhandarkar
> > Sent: Thursday, April 26, 2012 5:24 PM
> > To: llvmdev at cs.uiuc.edu
> > Subject: [LLVMdev] MemRefs in a Load Instruction
> >
> > Hi,
> >
> > On the hexagon target, I have written a following combiner pattern.
> > *********************************************
> >
> > def: Pat<(i64 (or (i64 (shl (i64 (extloadi32 (i32 (add IntRegs:$src1,
> >
> > s11_2ExtPred:$offset1)))),
> >                                                             (i32 32))),
> >                                     (i64 (zextloadi32
> ADDRriS11_2:$src2)))),
> >          (i64 (COMBINE_rr (LDriw_indexed IntRegs:$src1,
> > s11_2ExtPred:$offset1),
> >                                                (LDriw
> ADDRriS11_2:$src2)))>;
> > ******************************
> 
> I had to modify the above pattern where in the LDriw (the second load in
the
> COMBINE_rr) is changed to LDriw_indexed similar to the first load.
> I see the following in HexagonGenDAGISel.inc
> ***********************************************
> /*1161*/            OPC_EmitConvertToTarget, 2,
> 
> /*1163*/            OPC_EmitNode, TARGET_VAL(Hexagon::LDriw_indexed),
> 0|OPFL_Chain,
> 
>                         1/*#VTs*/, MVT::i32, 2/*#Ops*/, 1, 6,  // Results
=
> #7
> 
> /*1172*/            OPC_EmitConvertToTarget, 5,
> 
> /*1174*/            OPC_EmitNode, TARGET_VAL(Hexagon::LDriw_indexed),
> 0|OPFL_Chain,
> 
>                         1/*#VTs*/, MVT::i32, 2/*#Ops*/, 4, 8,  // Results
=
> #9
> 
> /*1183*/            OPC_MorphNodeTo, TARGET_VAL(Hexagon::COMBINE_rr),
> 0|OPFL_Chain|OPFL_MemRefs,
> ***********************************************
>
I saw that this problem is reported as PR 9947
(http://llvm.org/bugs/show_bug.cgi?id=9947). There, Cameron mentions that
the case with instructions having multiple references to memory will require
a separate fix.

Cameron - Is this bug / fix there somewhere ? Or can you advise me on
working on a fix myself ?

Pranav
Qualcomm Innovation Center, (QuIC) is a member of the Code Aurora Forum.