[LLVMdev] PreRASched

[Andrew Trick]

On Apr 27, 2012, at 7:49 AM, Jonas Paulsson wrote:

> Hi,
>  
> I wonder when the preRASched pass is planned to be available?
>  
> I wonder how one would best try to implement a pass in between RegCoalescer and RA. After RegCoalescer, the LiveVariables information seems broken (there are no Kills anywhere), and LiveVariables can’t be rerun after SSA form is left. So, how could one rebuild LiveIntevals? For register allocation purposes – what would be the best way to rebuild LiveIntervals after a rescheduling that demands a rerun of SlotIndexes? Is this a simpler task now that RegCoalescer is not in need of any info anymore? Could perhaps LiveIntervals be built without LiveVariables then?
> 

Hi Jonas,

We do plan to remove LiveIntervalAnalysis' dependence on LiveVariables. Much of the logic exists with regalloc, but there hasn't been a pressing need to factor it into a standalone, global pass.

If simply want to reschedule, then you can plug into, or follow the example of the MachineScheduler and call "handleMove" to update LiveIntervals.

Eventually, we'd like to be able to update LiveIntervals incrementally after modifying some well defined fragment of the instruction stream, but that functionality doesn't exist yet.

You can expect to see a decent amount of progress in these areas over the next few months.

-Andy
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