[LLVMdev] Registers and isel type inference

David A. Greene greened at obbligato.org
Mon Sep 26 14:35:47 PDT 2011

Jakob Stoklund Olesen <stoklund at 2pi.dk> writes:

>>> - Disable type inference for individual registers entirely, or
>>> - Add a ValueType field to the Register tablegen class, so types are
>>>  not inferred by enumerating register classes.
>> I tend to think the second would be preferable, but how would we handle
>> registers than can hold different types of values?
> AFAIK, the type inference is only a convenience, you can always use
> explicit casts to get at the other types.

True.  Wouldn't that also work for implicit defs?

> It's the use of HasOneImplicitDefWithKnownVT() that scares me, I don't
> think there is any workaround for that.

Can you explain more?  I'm not quiet following.  What workaround is
needed?  Are you saying that in the current system it's broken because
it relies on a single type for a register or that replacing it with
something in a new scheme won't be possible?


> /// HasOneImplicitDefWithKnownVT - If the instruction has at least one
> /// implicit def and it has a known VT, return the VT, otherwise return
> /// MVT::Other.
> MVT::SimpleValueType CodeGenInstruction::
> HasOneImplicitDefWithKnownVT(const CodeGenTarget &TargetInfo) const {
>   if (ImplicitDefs.empty()) return MVT::Other;
>   // Check to see if the first implicit def has a resolvable type.
>   Record *FirstImplicitDef = ImplicitDefs[0];
>   assert(FirstImplicitDef->isSubClassOf("Register"));
>   const std::vector<MVT::SimpleValueType> &RegVTs =
>     TargetInfo.getRegisterVTs(FirstImplicitDef);
>   if (RegVTs.size() == 1)
>     return RegVTs[0];
>   return MVT::Other;
> }

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